1. ) Field of the Invention
The present invention relates to a cache memory and a method for controlling a cache memory.
2. ) Description of the Related Art
In recent years, a cache memory is used in solving the problem of data delay between a central processing unit (CPU) and a main memory. The cache memory itself has a layered structure, and presently a plurality of cache memories is used. A first level cache and a second level cache are classified sequentially from the cache memory, which functions nearly as speedily as the CPU.
The conventional cache memory holds a copy of a tag relating to the first level cache in the second level cache, and the second level cache uses the copy of the tag to obtain information from the first level cache, thereby eliminating relating contradictions between the first level cache and the second level cache.
For example, as shown in FIG. 11, when a tag of the second level cache is accessed by a physical index, a copy of the tag of the first level cache is accessed by using a virtual index included in the second level cache, and coherence is maintained between the two by obtaining the registration status of the first level cache.
A technique for increasing the decoding efficiency of the cache line status by correlating a status bit field or the like against cache lines included in the cache is disclosed in, for example, Japanese Patent Application Laid-open No. H10-301850 Publication. A technique for enabling incorporation of the data cache to be reliably tracked by providing a directory including incorporation bits, command bits, and data bits, in a common second level cache is disclosed in, for example, Japanese Patent Application Laid-open No. H8-235061 Publication.
However, the conventional art has a problem that the speed of the machine cycle of the cache memory cannot be increased.
More specifically, when the second level cache obtains registration information from the first level cache so as to eliminate contradictions between the first level cache and the second level cache, a delay is caused because the tag is accessed in two stages.
Although there has been a notable increase in the processing speeds of CPUs in recent years, the CPU is encumbered by the slow processing speed of the cache memory that passes data to the CPU, making the problem of cache memory delay even more serious.
It is important to eliminate delay that arises when obtaining registration information from the first level cache, and increase the machine cycle speed.
The present invention has been achieved in order to solve the above problems of the conventional art, and aims to provide a cache memory and method for controlling a cache memory that can eliminate delay arising in the cache memory and increase the machine cycle speed.